1. Technical Field
The present invention relates to a Liquid Crystal Display (LCD), and more particularly, to an output buffer of a source driver included in an LCD having a high slew rate and a method of controlling the output buffer.
2. Discussion of the Related Art
An LCD is one of the most widely used flat panel displays because of its small-size, thinness and low power consumption. For example, an LCD is commonly found in a variety of electronic devices such as flat screen televisions, notebook computers, cell phones and digital cameras.
There are two main types of LCDs used in the market; they are passive matrix and active matrix. Because active matrix type LCDs use thin-film transistors as their switching devices, which enable products to be developed that have very good image quality, wide color gamut, and response time, they are increasingly becoming the choice of notebook computer and flat screen television manufacturers.
FIG. 1 is a block diagram illustrating a conventional active matrix type LCD 100. Referring to FIG. 1, the LCD 100 includes a liquid crystal panel 110, source drivers SD for driving a plurality of source lines SL, and gate drivers GD for driving a plurality of gate lines GL. It is noted that the source lines SL may also be referred to as data lines or channels.
The liquid crystal panel 110 includes a plurality of pixels 111. Each of the pixels 111 includes a switch transistor TR, a storage capacitor CST for reducing current leakage from a liquid crystal, and a liquid crystal capacitor CLC.
As shown in FIG. 1, the switch transistor TR is turned on/off in response to a signal received at a first terminal of the switch transistor TR for driving a gate line GL. A second terminal of the switch transistor TR is connected to a source line SL. The storage capacitor CST is connected between a third terminal of the switch transistor TR and a ground voltage VSS. The liquid capacitor CLC is connected between the third terminal of the switch transistor TR and a common voltage VCOM. Here, the common voltage VCOM may be half the value of a power supply voltage VDD.
FIG. 2 is a circuit diagram of a source driver (SD) 200 illustrated in FIG. 1. Referring to FIG. 2, the source driver 200 includes a digital-to-analog converter (DAC) 210, output buffers 220, output switches 230, and charge sharing switches 240.
The DAC 210 receives and converts a digital image signal D_DAT into analog image signals A_DAT1, A_DAT2, . . . , A_DATn. Each of the analog image signals A_DAT1, A_DAT2, . . . , A_DATn has a gray level voltage.
Each of the output buffers 220 amplifies a corresponding analog image signal A_DAT1, A_DAT2, . . . , A_DATn and outputs the amplified analog image signal to a corresponding output switch 230. The output switch 230 outputs the amplified analog image signal as one of a plurality of source line driving signals Y1, Y2, . . . , Yn in response to the activation of output switch control signals OSW and /OSW. Each of the source line driving signals Y1, Y2, . . . , Yn is supplied to a load LD connected to a source line SL.
As shown in FIG. 2, one of the loads LD is modeled by parasitic resistors RL1 through RL5 and parasitic capacitors CL1 through CL5, interconnected in the form of a ladder circuit.
Referring still to FIG. 2, the charge sharing switches 240 share charges stored in loads LD connected to the source lines SL in response to the activation of sharing switch control signals CSW and /CSW, thus precharging the source line driving signals Y1, Y2, . . . , Yn to a predetermined precharge voltage. If the voltage polarities of the source line driving signals Y1, Y2, . . . , Yn applied to neighboring source lines SL are opposite to each other, the precharge voltage may be VDD/2. For example, if a voltage of a first source line driving signal Y1 has a positive polarity voltage between VDD and VDD/2 and a voltage of a second source line driving signal Y2 has a negative polarity voltage between VDD/2 and VSS (e.g., a ground voltage), the precharge voltage may be VDD/2.
The charge sharing switches 240 control the voltages of each of the source line driving signals Y1, Y2, . . . , Yn to be VDD/2 during a charge sharing period before the output switches 230 are turned on. In other words, the voltage of each of the source line driving signals Y1, Y2, . . . , Yn is precharged to VDD/2, and the output switches 230 are turned on to supply the driving signals amplified by the output buffers 220 to their corresponding loads LD.
FIG. 3 is a circuit diagram of the conventional output buffer 220 shown in FIG. 2. Referring to FIG. 3, the output buffer 220 is implemented by a rail-to-rail operational amplifier.
The output buffer 220 includes an input section 221, an amplifier section 223, a capacitor section 225, and an output section 227. Here, the output buffer 220 has a voltage follower configuration in which an output signal OUT is fed back as a second input signal INN. A first input signal INP is an analog image signal and the second input signal INN is a source line driving signal.
The input section 221 includes first through third PMOS transistors MP1 through MP3 and first through third NMOS transistors MN1 through MN3, and receives the first input signal INP and the second input signal INN, which are complementary signals. A first bias voltage VB1 is applied to the gate of the first PMOS transistor MP1 and a sixth bias voltage VB6 is applied to the gate of the third NMOS transistor MN3.
The amplifier section 223, which is a folded cascode section, includes fourth through ninth PMOS transistors MP4 through MP9, and fourth through ninth NMOS transistors MN4 through MN9, and receives output signals of the input section 221 to amplify the input signals INP and INN. A second bias voltage VB2 is applied to the gates of the sixth and seventh PMOS transistors MP6 and MP7 and a third bias voltage VB3 is applied to the gates of the eighth and ninth PMOS transistors MP8 and MP9. A fourth bias voltage VB4 is applied to the gates of the fourth and fifth NMOS transistors MN4 and MN5 and a fifth bias voltage VB5 is applied to the gates of the sixth and seventh NMOS transistors MN6 and MN7.
The capacitor section 225 includes two capacitors Cp and stabilizes the frequency characteristics of the output signal OUT. The capacitor section 225 controls the output signal OUT of the output buffer 220 so that is does not oscillate. The capacitor section 225 is also called a ‘Miller compensation capacitor’.
The output section 227 includes a PMOS transistor MP10 and an NMOS transistor MN10, receives output signals of the amplifier section 223 and generates the output signal OUT of the output buffer 220. The output signal OUT is a source line driving signal.
A slew rate SR of the output voltage of the conventional output buffer 220 can be calculated using Equation 1 shown below.SR=dVout/dt=(IMP1+IMN3)/2C,  (1)
where, Vout is the output voltage of the output buffer 220, IMP1 is an amount of current flowing through the first PMOS transistor MP1, IMN3 is an amount of current flowing through the third NMOS transistor MN3, and C is the total capacitance of the capacitor Cp included in the capacitor section 225.
Since the conventional output buffer 220 has the constant capacitance C, the slew rate SR of the output voltage cannot be easily enhanced. For this reason, a source driver using the conventional output buffer 220 is unsuitable for a large-sized liquid crystal panel having source lines with large loads. Accordingly, there is a need for an output buffer for use with a source driver in an LCD that is capable of obtaining an enhanced slew rate.